Semiconductor chips permit the microfabrication of electric circuits and systems of circuits (including subcircuits, portions of circuits, circuit elements, and components of circuits) on a single monolithic substrate containing an ever increasing density of circuits and systems. With an increase in the functionality of semiconductor chips, over recent years, the available surface area of semiconductor chips, remaining for interconnections to be made, is thus increasingly crowded.
In part to relieve this crowding, semiconductor chip size has increased dramatically. Nonetheless, despite the increase in chip size, an unacceptably increased percentage of total chip "real estate" is now devoted to intra-chip interconnection of circuits and systems on the surface of the same semiconductor chip which is to carry the completed electric circuits and/or circuit systems.
One solution, albeit a not comprehensively successful approach, to the problem of crowding in semiconductor chips has been to increase the number of metal layers on semiconductor chips. With increased layers, the total chip real estate available to accomplish interconnections is increased substantially, in fact up to a multiple of integer values equal to the total number of layers selected to enhance the interconnection capabilities of the semiconductor chip. Each such film layer is, for example, on the order of one or two microns thick. However, there is a limit to the number of such metal layers that can effectively be fabricated on a single semiconductor chip. For example, fabrication of more than two or three superimposed metal layers with insulative layers or regions interposed therebetween during the wafer stage of manufacture has been known to cause unacceptable levels of increased wafer bow, thereby effectively reducing wafer yield.
Reducing the line width of conductive leads or providing additional area for interconnections, on the other hand, either increases conductive line resistance or consumes additional space which would otherwise desirably be allocated for use as a site of functional circuitry. Increased line resistance is caused by reducing interconnection line width and this of course reduces the speed of the semiconductor chip and requires stronger circuit drivers to be employed to drive the circuitry and systems on the semiconductor chip. This in turn increases power losses and makes the semiconductor chip run hotter than desired, which thus makes the chip useless for many applications or makes it necessary to provide elaborate heat removal features to the arrangement in which the chip is integrated. It is clear that the task of optimizing interconnection schemes for the semiconductor chip actually containing electric circuits and systems of circuits faces ever increasing obstacles.
It is accordingly an object of the invention to establish an interconnection arrangement and technique for interconnecting incomplete circuits, subcircuits, portions of circuits, and/or circuit elements and components on a single semiconductor chip, which interconnection arrangement is structurally monolithic, independent of, and separable from the semiconductor chip requiring interconnection.
It is another object of the invention to establish an interconnection arrangement for circuits, subcircuits, portions of circuits, and/or circuit elements and components fabricated on a single semiconductor chip, which arrangement is mountable on the semiconductor chip containing the circuitry to be interconnected.
It is another object of the invention to reduce the interconnection path lengths between circuits, subcircuits, portions of circuits, and circuit elements and components on a single semiconductor chip, whereby the amount of power lost in circuit operations and the amount of heat generated are reduced.
It is a further object of the invention to establish an interconnection arrangement for a single semiconductor chip containing incomplete electric circuits or systems of circuits, which relieves circuit crowding on the semiconductor chip and which accomplishes external, i.e., extra-chip interconnection to close gaps in circuits or systems of circuits on the chip with a monolithic, layered arrangement of conductive and insulative layers of material.